AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents

AutoSizer introduces a novel LLM-driven meta-optimization framework that automates transistor sizing in analog and mixed-signal circuits, addressing a critical bottleneck in chip design. The system uses a two-loop approach combining circuit understanding with adaptive search refinement, outperforming traditional EDA methods and existing LLM agents on a new 24-circuit benchmark.

AutoSizer represents a meaningful advancement in applying large language models to computational design problems that require both reasoning and numerical precision. The chip design industry has long struggled with transistor sizing due to the inherent complexity of nonlinear behavior across high-dimensional design spaces, typically requiring senior engineers months to optimize a single circuit. This research demonstrates how LLMs can serve as intelligent orchestrators rather than direct optimizers, leveraging their reasoning capabilities to guide and refine the search process rather than attempting numerical optimization directly.

The innovation lies in the two-loop architecture: an inner loop handles circuit sizing through simulation feedback, while an outer loop analyzes optimization dynamics to intelligently reconstruct the search space. This mirrors human design methodology, where experienced engineers iteratively refine their approach based on simulation results. The introduction of AMS-SizingBench, an open benchmark with 24 diverse circuits in SKY130 technology, provides the semiconductor research community with standardized evaluation criteria, accelerating future development in this space.

For the semiconductor and EDA industries, AutoSizer signals a shift toward AI-augmented design automation that could significantly reduce time-to-market and design costs. This has implications for fabless design companies and chipmakers seeking competitive advantages through faster iteration cycles. The framework's success on realistic simulator-based constraints suggests practical applicability rather than theoretical elegance. As semiconductor complexity continues increasing and design cycles compress, such AI-driven meta-optimization approaches may become industry standard, potentially reshaping EDA tool requirements and hiring practices in chip design teams.

• →AutoSizer uses a two-loop LLM framework that combines reasoning with adaptive search-space refinement for circuit optimization
• →The system outperforms traditional EDA methods and competing LLM agents across varying circuit difficulties
• →AMS-SizingBench provides an open benchmark of 24 diverse circuits for standardized evaluation of analog design automation
• →The approach treats LLMs as intelligent orchestrators rather than direct optimizers, addressing their precision limitations
• →Faster convergence and higher success rates suggest practical viability for accelerating semiconductor design workflows