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Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
🤖AI Summary
Researchers developed a runtime-reconfigurable bitwise systolic array architecture for multi-precision quantized neural networks on FPGA hardware accelerators. The system achieves 1.3-3.6x speedup on mixed-precision models while supporting higher clock frequencies up to 250MHz, addressing the trade-off between hardware efficiency and inference accuracy.
Key Takeaways
- →New bitwise systolic array design enables runtime reconfiguration for multi-precision quantized neural networks on hardware accelerators.
- →Implementation on Ultra96 FPGA platform demonstrates 1.3185 to 3.5671 times speedup for mixed-precision model inference.
- →Architecture supports higher clock frequency up to 250MHz with reduced critical path delay.
- →Mixed-precision quantization approach balances hardware resource consumption with inference accuracy.
- →Solution targets edge device applications including object tracking and image recognition.
#neural-networks#fpga#hardware-acceleration#quantization#edge-computing#systolic-array#mixed-precision#inference-optimization
Read Original →via arXiv – CS AI
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