VeriTrans: Fine-Tuned LLM-Assisted NL-to-PL Translation via a Deterministic Neuro-Symbolic Pipeline

VeriTrans is a machine learning system that converts natural language requirements into formal logic suitable for automated solvers, using a validator-gated pipeline to ensure reliability. Achieving 94.46% correctness on 2,100 specifications, the system combines fine-tuned language models with round-trip verification and deterministic execution, enabling auditable translation for critical applications.

VeriTrans addresses a fundamental challenge in formal verification: bridging the gap between human-readable specifications and machine-executable logic. By automating natural language-to-programming language translation with built-in validation mechanisms, the system tackles the error-prone manual translation process that currently limits adoption of formal methods in safety-critical domains. The round-trip verification approach—translating back from logic to natural language to confirm semantic preservation—demonstrates a practical architecture for catching translation errors before they propagate downstream.

The system's performance metrics reveal meaningful progress in reliability. The 94.46% correctness rate on SatBench, combined with 87.73% round-trip similarity, suggests the architecture effectively filters unreliable translations. Fine-tuning on modest example sets (100-150 curated cases) improves fidelity by 1-1.5 percentage points without latency penalties, indicating efficient learning. The thresholded acceptance policy creates a tunable reliability-coverage tradeoff, retaining 68% of inputs at 94% correctness—practically valuable for organizations prioritizing accuracy over throughput.

For reliability-critical workflows in hardware verification, smart contract auditing, and aerospace systems, deterministic execution with full auditability (temperature=0, seeded randomness, comprehensive logging) enables replay-driven debugging and regression testing—capabilities essential for certification and compliance. The validator contributing less than 15% runtime overhead suggests practical deployability without prohibitive computational costs.

Future developments should focus on expanding domain coverage beyond SatBench, improving coverage percentages at high confidence thresholds, and evaluating performance on complex real-world specifications. Integration with existing formal verification ecosystems and downstream solver optimization remain open questions.

• →VeriTrans achieves 94.46% SAT/UNSAT correctness by combining fine-tuned NL-to-logic translation with deterministic validation gates and round-trip verification
• →Compact fine-tuning on 100-150 examples improves translation fidelity by 1-1.5 percentage points without increasing system latency
• →Thresholded acceptance policies enable configurable reliability-coverage tradeoffs, retaining 68% of specifications at ~94% correctness when confidence threshold set to 75
• →Full artifact logging and deterministic execution (temperature=0, seed=42) enable replay-driven debugging and regression testing for certification-critical applications
• →Validator overhead contributes less than 15% of end-to-end runtime, making the system practical for production formal verification workflows