AINeutralarXiv – CS AI · 3h ago6/10
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AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
Researchers introduce AssertLLM2, an open-source benchmark containing 83 real-world hardware designs to evaluate how well Large Language Models can automatically generate formal SystemVerilog Assertions from specifications. The benchmark uniquely incorporates buggy RTL variants to assess both bug prevention and bug detection capabilities, establishing more rigorous evaluation standards for LLM-assisted hardware verification.