AINeutralarXiv – CS AI · 10h ago6/10
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A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
Researchers have developed a reconfigurable multiplier architecture for RISC-V processors that dynamically adjusts between exact and approximate computation modes to optimize energy efficiency in neural network inference. The design achieves 44-68% power reduction depending on mode while maintaining computational performance, with demonstrated energy consumption of 1.21 pJ/instruction for matrix multiplication operations.