5 articles tagged with #risc-v. AI-curated summaries with sentiment analysis and key takeaways from 50+ sources.
Researchers have developed ALADIN, a framework for analyzing accuracy-latency trade-offs in AI accelerators for embedded systems. The tool enables evaluation of quantized neural networks without requiring deployment on target hardware, potentially reducing development time and costs for AI chip designers.
Researchers have developed a reconfigurable multiplier architecture for RISC-V processors that dynamically adjusts between exact and approximate computation modes to optimize energy efficiency in neural network inference. The design achieves 44-68% power reduction depending on mode while maintaining computational performance, with demonstrated energy consumption of 1.21 pJ/instruction for matrix multiplication operations.
Researchers propose CUTEv2, a unified matrix extension architecture for CPUs that decouples matrix units from the pipeline to enable efficient AI workload processing across diverse architectures. The design achieves significant speedups (1.57x-2.31x) on major AI models while occupying minimal silicon area (0.53 mm² in 14nm), demonstrating practical viability for open-source CPU development.
SiFive, a RISC-V chip design startup, has raised $400M at a $3.65B valuation with participation from Nvidia, positioning itself to develop CPU architectures for AI data centers. The funding round signals Nvidia's strategic interest in diversifying chip architectures beyond its dominant GPU offerings and reflects growing competition in the AI infrastructure market ahead of SiFive's planned IPO.
Ethereum co-founder Vitalik Buterin has identified the state tree and virtual machine as Ethereum's primary bottlenecks, proposing solutions including binary state trees and a potential shift to RISC-V VM. These changes aim to enhance proving efficiency and simplify execution on the Ethereum network.
