Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification

Researchers propose a Knowledge Graph-based approach to improve AI-assisted formal verification of hardware designs, addressing the challenge of generating accurate SystemVerilog Assertions from natural-language specifications. By structuring design information from RTL code, specifications, and tool feedback into a queryable knowledge graph, the method achieves higher compilation success rates and formal coverage (78.5%-99.4%) while reducing syntax errors, though complex temporal reasoning remains challenging.

This research tackles a critical pain point in hardware verification where Large Language Models struggle to bridge the gap between high-level specifications and low-level Register Transfer Level implementations. Traditional approaches treat specifications and RTL as unstructured text, creating semantic mismatches that result in invalid assertions. The proposed Knowledge Graph framework restructures verification data into interconnected nodes linking requirements, design hierarchy, signals, and properties, enabling AI agents to retrieve contextually relevant information for assertion generation.

The multi-agent workflow represents a meaningful advance in formal verification automation, a domain where manual assertion writing consumes significant engineering resources. By incorporating feedback loops from formal tool diagnostics, counterexamples, and coverage reports, the system iteratively refines assertions rather than attempting single-pass generation. The approach demonstrates practical improvements in compilability and coverage rates across seven benchmark designs.

For the hardware and semiconductor industry, this work addresses persistent bottlenecks in formal verification, a process essential for ensuring correctness in critical designs. The integration of knowledge structures with LLM-based generation suggests broader applicability to other code synthesis problems requiring strong grounding in existing systems. However, the acknowledged limitations in handling complex temporal and arithmetic reasoning indicate that current AI capabilities cannot yet fully automate sophisticated verification tasks.

The research points toward hybrid human-AI verification workflows where AI assists in assertion generation while maintaining human oversight for complex properties. Continued advances in this direction could accelerate time-to-market for semiconductor designs and reduce verification costs, though autonomous formal verification of highly complex systems remains a frontier challenge.

• →Knowledge graphs improve AI assertion generation by structuring specification, RTL, and tool feedback into queryable design context
• →Multi-agent workflow with syntax repair, counterexample guidance, and coverage-directed loops reduces manual refinement overhead
• →Formal coverage ranges from 78.5% to 99.4% across benchmarks, demonstrating practical viability for hardware verification automation
• →Complex temporal and arithmetic reasoning remains a limitation of current LLM-based formal verification approaches
• →Framework suggests broader applicability to code synthesis problems requiring strong grounding in existing system architectures