3 articles tagged with #systemverilog. AI-curated summaries with sentiment analysis and key takeaways from 50+ sources.
Researchers have enhanced the Saarthi AI framework for formal verification, achieving 70% better accuracy in generating SystemVerilog assertions and 50% fewer iterations to reach coverage closure. The framework uses multi-agent collaboration and improved RAG techniques to move toward domain-specific AI intelligence for verification tasks.
Researchers introduce AssertLLM2, an open-source benchmark containing 83 real-world hardware designs to evaluate how well Large Language Models can automatically generate formal SystemVerilog Assertions from specifications. The benchmark uniquely incorporates buggy RTL variants to assess both bug prevention and bug detection capabilities, establishing more rigorous evaluation standards for LLM-assisted hardware verification.
Researchers propose a Knowledge Graph-based approach to improve AI-assisted formal verification of hardware designs, addressing the challenge of generating accurate SystemVerilog Assertions from natural-language specifications. By structuring design information from RTL code, specifications, and tool feedback into a queryable knowledge graph, the method achieves higher compilation success rates and formal coverage (78.5%-99.4%) while reducing syntax errors, though complex temporal reasoning remains challenging.
