Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA

Researchers have developed SECDA-DSE, a framework that integrates Large Language Models into FPGA accelerator design to automate hardware-software co-design exploration. The system successfully generated three different accelerator designs that were synthesized and executed on actual FPGA hardware, demonstrating LLM-guided design space exploration can reduce development time while capturing architecture-specific trade-offs.

SECDA-DSE represents a meaningful advancement in automating hardware accelerator design, traditionally a labor-intensive process requiring deep expertise in both software and hardware optimization. The framework addresses a real bottleneck in AI infrastructure development by leveraging LLMs to guide design space exploration through retrieval-augmented generation and chain-of-thought reasoning. This automation could democratize accelerator design by reducing dependency on specialized domain knowledge, potentially lowering barriers to entry for organizations developing custom AI hardware solutions.

The work builds on SECDA's existing capabilities for rapid hardware-software co-design and extends it by implementing an intelligent exploration layer. By successfully generating three distinct accelerator designs—element-wise vector multiplication, 2D convolution, and matrix transpose—and validating them on actual FPGA hardware, the researchers demonstrated proof-of-concept viability. The results show that automatically generated designs capture important kernel-specific architectural trade-offs, particularly between compute parallelism and memory bandwidth optimization.

For the hardware acceleration ecosystem, this approach addresses a critical challenge: as AI workloads become increasingly diverse and specialized, the demand for custom accelerators grows faster than human expertise can supply. Automated LLM-guided design exploration could accelerate development cycles, enabling faster iteration and broader exploration of the design space than manual methods. This capability becomes particularly valuable for emerging domains like edge AI and specialized scientific computing where generic accelerator designs prove suboptimal.

Future developments should focus on validating the framework across more complex workloads, improving design quality metrics beyond functional correctness, and establishing standards for LLM-guided hardware design. The approach could influence how hardware development integrates AI-assisted automation, potentially reshaping design methodologies across the accelerator industry.

• →SECDA-DSE successfully automates FPGA accelerator design exploration using LLM-guided reasoning and iterative refinement loops.
• →Generated accelerator designs were validated through end-to-end FPGA execution, demonstrating practical viability beyond simulation.
• →Automated design exploration captures architecture-specific trade-offs between parallelism and data movement across diverse workloads.
• →The framework reduces dependency on extensive hardware domain expertise, potentially accelerating accelerator development cycles.
• →LLM-guided design space exploration could address growing demand for specialized AI accelerators across diverse applications.