#hardware-software-codesign News & Analysis

4 articles tagged with #hardware-software-codesign. AI-curated summaries with sentiment analysis and key takeaways from 50+ sources.

4 articles

AIBullisharXiv – CS AI · Feb 277/107

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LLMServingSim 2.0: A Unified Simulator for Heterogeneous and Disaggregated LLM Serving Infrastructure

Researchers have released LLMServingSim 2.0, a unified simulator that models the complex interactions between heterogeneous hardware and disaggregated software in large language model serving infrastructures. The simulator achieves 0.97% average error compared to real deployments while maintaining 10-minute simulation times for complex configurations.

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AIBullisharXiv – CS AI · Jun 106/10

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Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA

Researchers have developed SECDA-DSE, a framework that integrates Large Language Models into FPGA accelerator design to automate hardware-software co-design exploration. The system successfully generated three different accelerator designs that were synthesized and executed on actual FPGA hardware, demonstrating LLM-guided design space exploration can reduce development time while capturing architecture-specific trade-offs.

AIBullisharXiv – CS AI · May 126/10

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TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators

Researchers have developed TRAM, a technique that jointly optimizes low-power approximate multiplier structures with AI model training parameters, achieving up to 27% power reduction in vision transformers without significant accuracy loss. This approach differs from prior methods by integrating hardware design with model training rather than designing multipliers separately.

AIBullisharXiv – CS AI · May 96/10

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LLM-Driven Design Space Exploration of FPGA-based Accelerators

Researchers present SECDA-DSE, an AI-driven framework that integrates Large Language Models into FPGA accelerator design to automate the complex process of hardware configuration optimization. The system combines structured design space exploration with LLM-powered reasoning and feedback loops, demonstrating practical feasibility through successful synthesis on a Zynq-7000 FPGA.