#semiconductor-design News & Analysis

5 articles tagged with #semiconductor-design. AI-curated summaries with sentiment analysis and key takeaways from 50+ sources.

5 articles

AIBullisharXiv – CS AI · Apr 147/10

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EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Models

EdgeCIM presents a specialized hardware-software framework designed to accelerate Small Language Model inference on edge devices by addressing memory-bandwidth bottlenecks inherent in autoregressive decoding. The system achieves significant performance and energy improvements over existing mobile accelerators, reaching 7.3x higher throughput than NVIDIA Orin Nano on 1B-parameter models.

🏢 Nvidia

AINeutralarXiv – CS AI · Jun 55/10

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Fault tolerance estimation in digital circuits with visualised generative networks

Researchers propose a novel computational method using Generative Adversarial Networks (GANs) to estimate fault tolerance in digital circuits. The approach compares ideal digital outputs against realistic signals to identify and quantify how various failure modes—such as missing or malfunctioning logical gates—affect circuit robustness.

AINeutralarXiv – CS AI · Jun 26/10

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PALTO: Physics-Informed Active Learning for Tri-Gate FinFET Design Optimization for Vertical Power Delivery

Researchers demonstrate a physics-informed machine learning framework called PALTO for optimizing GaN tri-gate FinFET designs in power delivery systems, achieving 2× better performance than industrial benchmarks through intelligent exploration of device parameters. The approach addresses computational limitations of traditional TCAD simulations while enabling discovery of optimal gate-to-drain configurations and channel thickness ratios.

AIBearisharXiv – CS AI · May 286/10

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When NPUs Are Not Always Faster: A Stage-Level Analysis of Mobile LLM Inference

A research study reveals that NPUs (Neural Processing Units) on mobile devices don't consistently accelerate LLM inference as expected, with CPUs outperforming NPUs on compute-intensive prefill operations and NPUs providing only marginal speedups on memory-bound decode stages. The findings challenge assumptions about heterogeneous mobile computing and suggest current NPU designs require architectural improvements for on-device AI workloads.

AINeutralarXiv – CS AI · May 116/10

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Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing

Researchers introduce PostEDA-Bench, a hierarchical benchmark for evaluating LLM-based agents in Electronic Design Automation tasks, specifically targeting Design Rule Check (DRC) fixing and Power-Performance-Area (PPA) optimization. Testing eight LLMs across 145 tasks reveals significant performance gaps, with best success rates of 36.66% for complex DRC reasoning and only 20% for multi-objective PPA optimization, indicating substantial room for improvement in AI-assisted chip design automation.