OpenURMA: A Clean-Room Open Implementation of the Unified Bus Protocol

OpenURMA is the first open-source implementation of Huawei's Unified Bus (UB) protocol, a 2025 specification designed to overcome RDMA bottlenecks at the network interface. The implementation demonstrates 4.37x lower latency and 2.80x higher throughput compared to RoCEv2, while consuming only 14% of FPGA resources, offering a potential architectural shift for datacenter networking.

OpenURMA addresses a fundamental architectural problem in modern datacenter RDMA systems. Current implementations like RoCE and InfiniBand maintain extensive per-connection state at the network interface and require multiple PCIe round trips for basic operations, creating latency and scalability constraints that don't match actual wire speeds. Huawei's Unified Bus protocol reimagines this by decoupling application endpoint state from transport state and enabling direct CPU load/store access to an on-chip bus controller, eliminating unnecessary abstraction layers.

This work builds on Huawei's Ascend 950 silicon, which shipped with closed-source UB support. The OpenURMA contribution matters because it provides the first independently verifiable, open implementation with transparent benchmarking against RoCEv2 baselines across multiple simulation tiers—RTL on FPGAs, SystemC simulation, and gem5 full-system modeling. The performance gains are substantial: 500 nanosecond end-to-end latency for 64-byte remote fetches versus 2186 nanoseconds on matched RoCEv2 configurations.

For the datacenter industry, OpenURMA signals that architectural alternatives to the inherited Queue Pair model merit serious attention. The FPGA efficiency (14% LUT utilization) suggests practical implementation feasibility. However, adoption depends on ecosystem factors: software stack maturity, vendor support beyond Huawei, and compatibility with existing datacenter infrastructure. The open implementation enables academic research and potential contributions from the broader systems community, potentially accelerating refinement and standardization of memory-access protocols.

• →OpenURMA delivers 4.37x latency reduction and 2.80x throughput improvement over RoCEv2 by eliminating PCIe round trips through native CPU load/store access.
• →Huawei's Unified Bus decouples per-application and per-transport state, reducing memory overhead from hundreds of megabytes at scale to a more manageable footprint.
• →The first clean-room open implementation provides transparent benchmarking across three simulation tiers, enabling independent verification unavailable with closed Ascend 950 silicon.
• →FPGA implementation uses only 14% of Xilinx Alveo U50 LUTs, suggesting practical hardware feasibility for datacenter deployment.
• →Success depends on ecosystem adoption beyond Huawei and integration with existing datacenter software stacks and management tools.